An adiabatic charging circuit is one method of reducing power consumption in MOS chip logic circuits, as proposed by Seitz, C. L., Frey, A. H., Mattisson, S., Rabin, S. D., Speck, D. A., and van de Snepscheut, J. L. A. in "Hot-Clock nMOS," Proceedings of the 1985 Chapel Hill Conference on VLSI, pp. 1-17 (Computer Science Press, 1985). The following will explain this adiabatic charging.
In charging the voltage of a certain node in a standard CMOS circuit, from the time the switch connected to the power source (MOSFET) is closed until the node (capacity C) is fully charged, the resistance of the switch results in the dissipation of (1/2).times.CV.sup.2 of energy, where V is the potential difference across the switch. However, when the potential of the node and the potential of the power source are equal, the current will not flow through the switch even when the power source and the node are connected through the switch, and there will accordingly be no dissipation of energy due to the resistance of the switch.
Accordingly, when the voltage of the power source is increased slowly in comparison with the time constant RC of the switch resistance R and the node capacitance C, it is possible to increase the potentials of the node and the power source in such a way that the potential difference across the switch is reduced and so that the potentials of the node and the power source remain close to one another. In this way, the potential of the node can be balanced with the power source, and the capacitance of the node can be charged adiabatically. In such a case, the energy dissipated by the resistance of the switch will be: ##EQU1## Here, T is the time necessary for this process, and V (t) is the voltage characteristic of the capacitance.
If the curve of the voltage is a line, R and T are constant, and T RC, then equation (1) above becomes analogous to equation (2) below: EQU E=(1/2).multidot.CV.sup.2 .multidot.(2RC/T) (2)
If the curve of the voltage is a sine wave, equation (2) above is multiplied by the coefficient .pi..sup.2 /8.
Equation (2) above shows that if T is increased infinitely, the amount of energy necessary to charge the node capacity can be reduced to zero. This method of quasi-static charging is the adiabatic charging referred to above. The amount of energy dissipated in this adiabatic charging is substantially different from that in standard CMOS charging, where, as noted above, (1/2).times.CV.sup.2 of energy is dissipated, regardless of time; i.e., regardless of constant RC.
For example, in the case of the CMOS inverter shown in FIG. 7, when input IN sent to input node KI changes as shown in FIG. 8(a), output OUT.sup.- from output node KO will change as shown in FIG. 8(b). More specifically, when the input IN falls from high level to low level at time t11, PMOS transistor QP is turned on, and NMOS transistor QN is turned off. Accordingly, the charging current (shown by reference symbol I1) from power line 1 flows through the PMOS transistor QP to charge the output node KO. The output node KO will be charged to the potential Vdd of the power source to which the power line 1 is connected.
In contrast, when the input IN rises from low level to high level at time t12, the PMOS transistor QP is turned off, and the NMOS transistor QN is turned on. The charge of the output node KO is discharged (as discharge current I2) through the NMOS transistor QN to power line 2.
Accordingly, in this kind of regular charging, as shown in FIG. 9, the energy loss due to switching results from the potential difference V1 between the fixed potential Vdd of the power source (shown by reference symbol .alpha.1) and the potential of the output node KO (shown by reference symbol .alpha.2). In contrast, in the adiabatic charging method mentioned above, the potential of the power source changes as shown by reference symbol .alpha.3, and accordingly the potential of the output node KO also changes as shown by reference symbol .alpha.4. Thus the energy loss is reduced to a small amount corresponding to the potential difference shown by reference symbol V2.
In recent years many MOS transistor circuits using this kind of adiabatic charging have been proposed, for example, Moon, Y. and Jeong, D.-K.: "Efficient Charge Recovery Logic," 1995 Symposium on VLSI Circuits: Digest of Technical Pacers, pp. 129-130 (May 1995), and Kramer, A., Denker, J. S., Flower, B., and Moroney, J.: "2nd Order Adiabatic Computation with 2N-2P and 2N-2N2P Logic Circuits," Porc. Int. Symp. Low Power Design, pp. 191-196 (Dana Point, April 1995). FIG. 10 shows MOS logic circuit F0, a typical example of this kind of conventional art.
This MOS logic circuit F0 is the inverter/buffer gate of a dual rail logic circuit called an "ECRL (Efficient Charge Recovery Logic) Circuit" or a "2N-2P Circuit." In brief, this MOS logic circuit F0 is arranged so that a serial circuit consisting of a PMOS transistor QP1 and an NMOS transistor QN1, and a serial circuit consisting of a PMOS transistor QP2 and an NMOS transistor QN2 are connected in parallel between power lines 1 and 2.
The gate electrodes of the NMOS transistors QN1 and QN2 are connected to a first input node KI1 and a second input node KI2, respectively; an input IN.sup.+ is applied to the gate electrode of the NMOS transistor QN1, and an input IN.sup.-, which is logic-inverted with respect to the input IN.sup.+, is applied to the gate electrode of the NMOS transistor QN2. The connection between the drain electrode of the PMOS transistor QP2 and the drain electrode of the NMOS transistor QN2 provides a first output node KO1, from which the output OUT.sup.+ is applied to the gate electrode of the PMOS transistor QP1, to which it is cross-connected. In the same way, the connection between the drain electrode of the PMOS transistor QP1 and the drain electrode of the NMOS transistor QN1 provides a second output node KO2, from which the output OUT.sup.- is applied to the gate electrode of the PMOS transistor QP2, to which it is cross-connected. The power line 1 is connected to a pulse power source .phi., the voltage output level of which changes between ground level and a fixed high level Vdd. The power line 2, on the other hand, is connected to the output of a constant-voltage power source, the output level of which is equal to the ground level.
FIG. 11 is a wave-form diagram showing the operation of the MOS logic circuit F0 arranged as described above. In this MOS logic circuit F0, the operations of one cycle consist of four operations: "RESET," "WAIT," "EVALUATE," and "HOLD." The wave forms of the input IN.sup.+, the input IN.sup.-, the pulse power source .phi., the output OUT.sup.+, and the output OUT.sup.- on FIG. 10 correspond to FIGS. 11(a), (b), (c), (d), and (e), respectively.
First, in the RESET operation, the change in the level of the pulse power source .phi. from high level to low level (see FIG. 11(c)) is accompanied by a drop to low level of the output nodes KO1 and KO2, thereby erasing the respective data of the output nodes KO1 and KO2 (see FIGS. 11(d) and (e)). Next, in the WAIT operation, the voltage output level of the pulse power source .phi. remains at low level, while the input to either one of the input nodes (in the example in FIG. 10, the input IN.sup.+ to the input node KI1; see FIG. 11(a)) rises from low level to high level.
After an input state is established in this way, the EVALUATE operation is performed, in which the pulse power source .phi. rises from low level to high level (see FIG. 11(c)). At this time, since, as stated above, the input IN.sup.+ is high level, and the input IN.sup.- is low level, the NMOS transistor QN1 is turned on, but the NMOS transistor QN2 is turned off; the PMOS transistor QP2 is turned on, and the level of the output OUT.sup.+ rises in response to the rise in the output voltage of the pulse power source .phi. (see FIG. 11(d)). Further, at this time, the MOS transistors QN2 and QP1 remain off, and the output OUT.sup.- remains at low level (see FIG. 11(e)).
After the potentials of the output nodes KO1 and KO2 are established, the HOLD operation is performed, in which both the input nodes KI1 and KI2 fall to low level, and the input data is erased (see FIGS. 11(a) and (b)). The gate electrodes of the PMOS transistors QP1 and QP2, as stated above, are cross-connected to the output nodes KO1 and KO2, and therefore when the inputs IN.sup.+ and IN.sup.- are erased, the NMOS transistors QN1 and QN2 are both turned off, but the high level of the output node KO1 is maintained (see FIG. 11(d)), and the low level of the output node KO2 is dynamically maintained because it is cut off from the constant-voltage power source.
In the next cycle, after performing a RESET operation in the same way, during a WAIT operation, the input IN.sup.- rises from low level to high level, and the input IN.sup.+ remains at low level. As a result, in the next HOLD operation, the output OUT.sup.- is maintained at high level (see FIG. 11(e)) and the output OUT.sup.+ is at low level (see FIG. 11(d)). The inverter/buffer operations are performed as described above.
By replacing the NMOS transistors QN1 and QN2, which are functional circuits, with the serial and/or parallel connections of a plurality of MOS transistors, a MOS logic circuit F0 can be a unit logic circuit capable of outputting the desired combinational logic in accordance with the above-noted connections. Further, a circuit can be structured in sequence using the unit logic circuits. For example, by using the inverter/buffer shown in FIG. 10 as a unit logic circuit, and connecting several such unit logic circuits in a multi-stage cascade, a sequential circuit such as that shown in FIG. 12 can be provided. Such a sequential circuit can be used, for example, as a shift register.
In the example shown in FIG. 12, inverter/buffers F1, F2, F3, and F4 are driven by pulse power sources .phi.1, .phi.2, .phi.3, and .phi.4, the phases of which are shifted 1/4 cycle away from one another. It is sufficient if the pulse power sources .phi.3 and .phi.4 have the opposite phases with respect to .phi.1 and .phi.2, respectively, so that .phi.3=.phi.1 and .phi.4=.phi.2. Inputs IN.sup.+ and IN.sup.- are sent to the first-stage inverter/buffer F1, and the output of each of the inverter/buffers F1, F2 and F3 is sent to the following inverter/buffer F2, F3, and F4, respectively. Outputs OUT.sup.+ and OUT.sup.- are outputted from the last-stage inverter/buffer F4.
A wave-form diagram of the operations of the pulse power sources .phi.1, .phi.2, .phi.3, and .phi.4 is shown in FIG. 13. Next, the operations of the inverter/buffers F1 through F4 at t0, t1, t2, and so on are shown in FIG. 14. In FIG. 14, "#1" shows the data of the first cycle, and "#2" shows the data of the second cycle. In this way, the data #1, #2, and so on are shifted sequentially to the following stages each 1/4 cycle, in synchronization with the cycles of the pulse power sources .phi.1 through .phi.4.
In the foregoing conventional MOS logic circuit, if the NMOS transistor QN1 or QN2 is turned on, the output node KO2 or KO1, respectively, will be maintained at low level. However, as mentioned above, during the HOLD operation, the input nodes KI1 and KI2 both fall to low level, and when the NMOS transistor QN1 or QN2 is turned off, whichever of the output nodes KO2 and KO1 is to output a low level is only maintained dynamically, and therefore is prone to be influenced by neighboring circuits, etc.
For example, in cases like the shift register shown in FIG. 12, each logic circuit connected in cascade becomes unstable due to the influence of logic switching in the neighboring circuit, thereby causing logic errors. This creates the problem of limitations in circuit design, such as not being able to place adjacent to one another circuits operated by pulse power sources of different phases; i.e., different pulse power sources.
Further, in the MOS logic circuit F0, as shown in FIG. 15, there are parasitic pn diodes shown by reference symbols D1 and D2 between the drain of the NMOS transistor QN1 and p well 5, and between the drain of the PMOS transistor QP1 and n well 6, respectively.
For this reason, when the RESET operation is performed when the output node KO2 is outputting a low level, since in the initial state of the RESET operation the pulse power source .phi. is high level and the input node KI1 low level, the pn diode D2 between the drain of the PMOS transistor QP1 and the p well 6 is reverse biased, and a charge is stored in the junction capacitance of the pn diode D2. Conversely, since the same potential is applied across the pn diode D1 between the drain of the NMOS transistor QN1 and the n well 5, no charge is stored in the junction capacitance of the pn diode D2.
Accordingly, when the pulse power source .phi. falls from high level to low level in the RESET operation, the charge stored in the junction capacitance of the pn diode D2 is distributed to the junction capacitance of the pn diode D1, and therefore the potential of the output node KO2 drops to a negative value, which is lower than the ground level which is the output level of the constant-voltage power source. Hence the problem arises that that much additional energy is required in recharging.
Other conventional art intended to solve this kind of problem is the 2N-2N2P circuit proposed in the paper by Kramer, et.al. referred to above. FIG. 16 is an electrical circuit diagram of a MOS logic circuit F10 of the type proposed by this other conventional art. In this MOS logic circuit F10, elements similar to and corresponding with those in the MOS logic circuit F0 shown in FIG. 10 will be given the same reference symbols, and explanation thereof will be omitted.
In this MOS logic circuit F10, NMOS transistors QN3 and QN4 are provided parallel to NMOS transistors QN1 and QN2, respectively. The gate electrode of the NMOS transistor QN3 is connected to the gate electrode of a PMOS transistor QP1, i.e., to an output node KO1, and the gate electrode of the NMOS transistor QN4 is connected to the gate electrode of a PMOS transistor QP2, i.e., to an output node KO2.
Accordingly, during the HOLD operation, when, for example, the output node KO1 is maintained at high level, the NMOS transistor QN3 is turned on, so even if the input IN.sup.+ drops to low level, the output node KO2 can be stably maintained at a low level. In this way, the MOS logic circuit F10 is arranged so that even if both the inputs IN.sup.+ and IN.sup.- fall to low level, the low-level output remains stable.
Further, when the RESET operation is performed when the output OUT.sup.- from the output node KO2 is at low level, the NMOS transistor QN3 is turned on, or if when the output OUT.sup.+ from the output node KO1 is at low level, the NMOS transistor QN4 is turned on, and in either case there will be no storage of a charge as shown in FIG. 15. Thus power consumption can be held to a minimum.
Although there is more freedom of design with the MOS logic circuit F10 because there is no influence from neighboring circuits, it has the problem that two additional NMOS transistors QN3 and QN4 per unit logic circuit are required, and that the size per unit logic circuit is increased by 6/4 times.